Advances in modern semiconductor device technology have allowed increasing numbers of devices and circuits to be fabricated within a single semiconductor chip. This has required increasing microminiaturization of the interconnection metallurgy system connecting the elements within the chip into circuits. Such miniaturization results in decreased costs and improved performance in integrated circuits but is constantly crowding the fabrication technology, particularly the photolithographic and etching techniques of the interconnection metallurgy.
In integrated circuit design, for example, thousands of impurity regions are conventionally fabricated in a silicon chip, approximately 125-200 mils square. Such regions form transistors, diodes, resistors and the like which are then connected together by thin film wiring patterns atop the chip to form various circuits and for connection to input-output terminals.
This interconnection thin film system atop the chip is extremely complex and usually employs two or three separate levels of complex conductive patterns, each separated by one or more layers of dielectric material. Ordinarily, the first level conductive pattern on the chip surface interconnects the transistors, resistors, diodes, etc. into circuits and also provides for circuit-to-circuit connection. The second level conductive pattern makes contact to the first level by wet or dry etched vias through an insulation layer. With the increase in circuit density such as 10k bit bipolar memories, via size is reduced to 5 .mu.m. Interfacial contaminant films (e.g. oxide) 20 A in thickness within such small vias become detrimental to circuit switching speeds. The second level conductive pattern conventionally completes the circuit-to-circuit connections and makes contact to I/O terminals which are connectable to a support such as a module, substrate or card. Alternatively, a third level may be required for power and I/O connections. Four levels of metallization may be required in future products.
Aluminum-copper metallurgy has been typically used in the prior art to avoid the electromigration problem, as is discussed, for example, by Hall et al, in U.S. Pat. No. 3,743,894.
In the fabrication of semiconductor device, a contact metal layer of aluminum is generally used to make ohmic contact to the device. When the device is operated under high current and high temperature conditions, the aluminum contact metal is transported by the current flowing therethrough causing the metal to build up in some areas and to form voids in others. The voids can become large enough to sufficiently increase the resistance of the metal contact in the area where the voids occur to allow resistive heating to cause the contact metal to melt, thereby causing premature failure of the device.
Hall et al teaches that to avoid the electromigration problem, aluminum contact metallization is codeposited with a small percentage of copper on the order of 1 to 10 percent by weight. Forming a fine grain structure of CuAl.sub.2 grains having a diameter of less than 1000A interspersed between aluminum grains at the grain boundaries and triple points thereof.
Silicon has been alloyed with the aluminum-copper in the prior art to prevent the aluminum-copper from penetrating into the silicon substrate as is discussed, for example, by Kuiper in U.S. Pat. No. 3,382,568.
The use of aluminum/copper alloys and their methods of deposition are also discussed in U.S. Pats. No. 3,631,305, No. 3,716,469, No. 3,743,894, No. 3,725,309, No. 3,830,657, No. 3,987,216, No. 4,062,720, No. 4,070,501 and No. 4,184,909, which are illustrative of this art.
The addition of copper in aluminum and its deposition by conventional techniques employed heretofore results in metallization highly susceptible to corrosion during semiconductor processing and as well in the formation of large Al.sub.2 Cu intermetallics. The preferential formation of Cu rich regions on the metallization surface accelerates oxide growth and corrosion products during normal processing steps or stages. Local Al.sub.2 Cu cells set up by the differences in the electromotive series between Al and Cu rich regions form galvanic cells which exacerbate the problem.
It has been found that conventional aluminum/copper metallurgy techniques employed heretofore, result in the formation of copper rich intermetallics (Al.sub.2 Cu) on the film surface which result in high resistance regions which detract from the operability of the devices as well as reducing yield. The severity of the problem is particularly critical with use of multilevel metallurgy where it is necessary to interconnect the levels at appropriate points, where a high copper concentration occurs at the interfaces of those multilevel interconnections during normal device processing. Such high copper concentrations result in high ohmic connections, which affect circuit functionality. Also, it has been found that with multilevel product, the addition heat treatments (of normal processing) results in formation of intermetallics which in time, will traverse the entire metallurgical structure thus causing field failure.
Further the presence of large areas of copper rich intermetallics on the film surface is a significant factor in causing high resistance vias (e.g. the interconnection points of multilevel metallurgy). The region preferentially grow a thick oxide layer during quartz or SiO.sub.2 deposition which is extremely difficult to remove during sputter etch cleaning. The thick oxide results in a high via resistance.